This invention relates to an area solid-state imaging device of the type in which an array of picture elements of photodiodes and insulated gate field effect transistors (hereinafter, referred to as MOST) is vertically scanned by a shift register and horizontally scanned by a charge transfer device (hereinafter, referred to as CTD).
Two types of the solid-state imaging devices are known: the MOS type using insulated gate field-effect transistors and the CTD type using charge transfer devices. The former, or the MOST type makes effective use of light of the image and produces a large amount of signal charge. On the other hand, the MOST type generates a higher noise during reading than the CTD type. Thus, both types have an advantage and a disadvantage.
A solid state imaging device with the advantages of these two types has been proposed in which its light-sensitive portion is of the MOS type and its read register is of the CTD type, as shown in FIG. 1.
FIG. 1 schematically shows one example of a conventional solid-state imaging device having a photodiode array for the light-sensitive portion and a read register CTD. Referring to FIG. 1, there are shown an input device 11 of CTD, an output device 12 thereof, a charge transfer device 13 thereof, photodiodes 14, vertical switch MOSTs 15, vertical signal lines 16, a vertical scanning circuit 17 and transfer gates 18.
In operation of FIG. 1, signal charges on the vertical signal lines 16 are transferred to the CTD during the horizontal blanking period. When the potential of a certain vertical gate line 10 is high in the horizontal blanking period, the signal charges of the photodiodes in a row are transferred to the vertical signal lines 16. Then, when the shift pulse at the transfer gates 18 (TX) and CTD 13 becomes high level, the signal charges on the vertical signal lines 16 flow toward the CTD 13. At the last time of transferring, the vertical signal lines 16 are clamped at a potential V.sub.c as defined by EQU V.sub.c =V.sub.T -V.sub.th (TX) (1 )
where V.sub.T represents the high-level voltage at the transfer gates TX, and V.sub.th (TX) is the effective threshold voltage including the substrate biasing effect, at the transfer gates TX.
This example of the conventional imaging device of the compromise type between the MOS type and CTD type was expected to have excellent performance, but actually achieved only quite satisfactory performance for the following reasons.
When the charges on the vertical signal lines are transferred to the CTD, random noise (thermal noise) as expressed by Eq. (2) is caused by the fluctuation of the high-level voltage at the transfer gate which determines the clamp potential on the vertical signal lines: EQU &lt;q.sup.2 &gt;=1/2S.sub.u (O)C.sub.v.sup.2 /t (2)
where S.sub.u (O) is the power spectrum of the fluctuation of clock, C.sub.v the electrostatic capacitance of the vertical signal line and t the transfer time.
For example, in the common pulse drive method, the noise current is about 2.2 nA under .sqroot.S.sub.u (O)=0.7 .mu.V/.sqroot.Hz (S/N=100 dB at 15 kHz and 10-V amplitude). C.sub.v =1.6 pF and t=2 .mu.sec.
In order to reduce this noise, it is necessary to decrease the fluctuation of the voltage at transfer gates upon switching on, which determines the clamp potential on the vertical signal lines.
In the Japanese utility model application laid-open No. 78364/1981 (laid-open on June 25, 1981) there is disclosed another example of the solid-state imaging device using a photodiode array for the light sensitive portion and a CTD for the read register. This device has a blooming preventing circuit as shown in FIG. 2. Referring to FIG. 2, there are shown input devices 21A and 21B of the CTD, output devices 22A and 22B thereof, charge transfer devices 23A and 23B thereof, photodiodes 24, vertical switch MOSTSs 25, vertical signal lines 26, a vertical scanning circuit 27, first transfer gates 28A and 28B, second transfer gates 29A and 29B and blooming preventing circuits 30A and 30B. The operation of this imaging device will hereinafter be described. FIG. 3 is a timing chart of the pulses in the solid-state imaging device of FIG. 2.
The CTD operates in the horizontal scanning period to transfer each signal to the output stage, and at the same time constant bias charges are transferred in turn from the input device. At the end of the horizontal scanning period, all the signals have been read and a constant amount of charge CG exists at each stage of the CTD.
At the start of the horizontal blanking period, A-channel operation begins. When the pulse TX2 and BLG in FIG. 2 become high level and the pulse BLD therein is at low level, the charges from the BLD line flow into the vertical signal line. Then, when the BLD is made high level, the charges conversely flow from the vertical signal line to the BLD line, and the vertical signal line is clamped at a potential V.sub.vc expressed by the following equation to stop the current flow: EQU V.sub.vc =V.sub.TX2 -V.sub.thTX2 ( 3)
wherein V.sub.TX2 and V.sub.thTX2 represent the high-level voltage on the TX2 and the effective threshold voltage at the TX2 gate 29, including substrate biasing effect, respectively.
The BLG becomes low level, and the BLG and BLD do not participate in the following operations. Then, the TX1 becomes high level, and when the shift pulse H1 to the CTD is made low level, each bias charge CG sent from the input device of the CTD is transferred to the respective vertical signal lines. When the H1 is low level, the charge must be prevented from shifting to the adjacent electrode to the CTD by properly setting up the potential relation. Specifically, if the threshold voltage of the CTD channel, the threshold voltage of the transfer gate TX1, the low level of the shift pulse H2 to the CTD and the high level of the transfer pulse TX1 are represented by V.sub.thC, V.sub.thTX1, H.sub.2L and V.sub.TX1, respectively, it is necessary to satisfy the condition given by EQU V.sub.TX1 -V.sub.thTX1 .gtoreq.H.sub.2L -V.sub.thc ( 4)
At this time, when the potential V.sub.20 on a vertical gate line (at 20 in FIG. 2) becomes high level, the signal charges in the photodiodes on a row are transferred to the vertical signal lines to mix with the bias charges from the CTD.
When the shift pulse H1 to the CTD is at high level, the bias charge and signal charge on the vertical signal line flow to the CTD until the vertical signal line reaches the potential V.sub.vc expressed by Eq. (3).
When the transfer pulse TX1 is made low level, the vertical signal line is electrically disconnected from the CTD, and at this time the bias charge at the CTD is added with the signal charge from the photodiode.
Although signals on the nth row are fed to the A-channel CTD as described above, signals on the (n+1)th row are transferred to the other B-channel CTD in the second half of the horizontal blanking period as in the A-channel. Thus, the CTDs of A- and B-channels are operated in the horizontal period, so that signals on two rows are read in turn from the two output stages. This type of solid-state imaging device can thus read two rows at a time. Of course, provision of only A-channel will result in the solid-state imaging device of one-row reading type.
In this conventional imaging device, if the respective vertical signal lines are set at the clamp potential as in Eq. (3) at each channel by the BLD and BLG before the signals are read, it will be expected to remove the adverse effects of the threshold voltage fluctuation at the second transfer gates of A- and B-channels over 10 mV to 100 mV and the threshold voltage fluctuation on the vertical signal lines. In addition, an excellent characteristic will be expected from the combination of the advantages of the MOS and CTD types. In practice, however, random noise is caused by the pulse drive of the second transfer gate and thus no satisfactory characteristics can be obtained as in the example of FIG. 1.